Datasheet

55.2 Embedded Characteristics
• DMA AHB Master Interface
•
Supports Monitoring of up to 4 Non-Contiguous Memory Regions
• Supports Block Gathering Using Linked Lists
• Supports Secure Hash Algorithm (SHA1, SHA224, SHA256)
• Compliant with FIPS Publication 180-2
• Configurable Processing Period:
– When SHA1 algorithm is processed, the runtime period is either 85 or 209 clock cycles.
– When SHA256 or SHA224 algorithm is processed, the runtime period is either 72 or 194 clock cycles.
• Programmable Bus Burden
55.3 Block Diagram
Figure 55-2. Integrity Check Monitor Block Diagram
Integrity
Scheduler
SHA
Hash
Engine
Host
Interface
Context
Registers
Monitoring
FSM
Configuration
Registers
Master
DMA Interface
APB
Bus Layer
SAM E70/S70/V70/V71 Family
Integrity Check Monitor (ICM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1744