Datasheet

53.7.9 DACC Interrupt Disable Register
Name: DACC_IDR
Offset: 0x28
Reset: –
Property: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No ef
fect.
1: Disables the corresponding interrupt.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
EOC1 EOC0 TXRDY1 TXRDY0
Access
W W W W
Reset 0 – 0 –
Bits 4, 5 – EOCx End of Conversion Interrupt Disable of channel x
Bits 0, 1 – TXRDYx T
ransmit Ready Interrupt Disable of channel x
SAM E70/S70/V70/V71 Family
Digital-to-Analog Converter Controller (DACC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1723