Datasheet

53.7.5 DACC Channel Disable Register
Name: DACC_CHDR
Offset: 0x14
Reset: –
Property: Write-only
This register can only be written if the WPEN bit is cleared in the DACC W
rite Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
CH1 CH0
Access
W W
Reset 0 –
Bits 0, 1 – CHx Channel x Disable
WARNING
If the corresponding channel is disabled during a conversion or if it is disabled then re-enabled during a
conversion, its associated analog value and its corresponding EOC flags in DACC_ISR are unpredictable.
Value Description
0
No effect.
1
Disables the corresponding channel.
SAM E70/S70/V70/V71 Family
Digital-to-Analog Converter Controller (DACC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1719