Datasheet

When the FIFO is full or the DACC is not ready to accept conversion requests, the TXRDY flag is inactive.

The DACC also of

fers the possibility of writing two data words in one access by setting the bit WORD in the

DACC_MR. In this case, bits 11:0 contain the first data to be converted and bits 27:16 contain the second data to be

converted. The two data are written into the FIFO of the selected channel. The TXRDY flag takes into account this

double write access. Changing this access mode implies first switching off all channels.

WARNING

Writing in DACC_CDRx while TXRDY flag is inactive will corrupt FIFO data.

53.6.6 Register Write Protection

To prevent any single software error from corrupting DACC behavior, certain registers in the address space can be

write-protected by setting the WPEN bit in the DACC W

rite Protection Mode Register (DACC_WPMR).

If a write access to a write-protected register is detected, the WPVS bit in the DACC Write Protection Status Register

(DACC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.

The WPVS bit is automatically cleared after reading the DACC_WPSR.

The following registers can be write-protected :

• DACC Mode Register

• DACC Channel Enable Register

• DACC Channel Disable Register

• DACC Analog Current Register

• DACC Trigger Register

SAM E70/S70/V70/V71 Family

Digital-to-Analog Converter Controller (DACC)

echnology Inc.

Datasheet

DS60001527D-page 1712