Datasheet
When set to Single-ended mode (DIFF = 0), each DAC channel can be configured independently.
When set to Dif
ferential mode (DIFF = 1), the analog outputs DACP and DACN are located on DAC0 and DAC1
outputs, respectively. All operations are driven by channel 0 and activating this channel automatically activates
channel 1. Sending a value on channel 0 (DACP) automatically generates the complementary signal to be sent to
channel 1 (DACN). The signal sent to the DAC is centered around 2048. For example, sending 3000 = 2048 + 952 to
the DAC0 channel will automatically send 1096 = 2048 - 952 to the DAC1 channel.
53.6.4 Conversion Modes
The conversion modes available in the DACC are described below.
53.6.4.1 Trigger Mode
Trigger mode is enabled by setting DACC_TRIGR.TRGENx.
The conversion waits for a rising edge on the selected trigger to send the data to the DAC. In this mode, the
maximum data rate (i.e., the maximum trigger event frequency) cannot exceed 12 DAC clock periods plus 2 cycles of
resynchronization stage.
Note: Disabling Trigger mode (TRGENx = 0) automatically sets the DACC in Free-running or Max speed mode
depending on the status of DACC_MR.MAXSx.
Figure 53-2. Conversion Sequence in Trigger Mode
Write DACC_CDR0
DAC Channel 0
Output
EOC0
(not required by
software)
d0 d1
d0
d1
TXRDY
(used by software)
FIFO 0
is ready
d2 d3
FIFO 0
is full
d2
SOC0
d4
FIFO 0
is empty
DAC conversion
period
Trigger event
DAC conversion
period
d0
DAC conversion
period
d1
Trigger Period
53.6.4.2 Free-Running Mode
Free-running mode is enabled by clearing DACC_TRIGR.TRGENx and DACC_MR.MAXSx.
The conversion starts as soon as at least one channel is enabled. Once data is written in the DACC Conversion Data
Register (DACC_CDRx),
12 DAC clock periods later, the converted data is available at the corresponding analog
output. The next data is converted only when the EOC of the previous data is set.
If the FIFO is emptied, no conversion occurs and the data is maintained at the output of the DAC.
SAM E70/S70/V70/V71 Family
Digital-to-Analog Converter Controller (DACC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1708