Datasheet

53.5 Product Dependencies
53.5.1 I/O Lines
The digital input DATRG is multiplexed with digital functions on the I/O line and is selected using the PIO Controller.
The analog outputs DAC0/DACP
, DAC1/DACN are multiplexed with digital functions on the I/O lines .The analog
outputs of the DACC drive the pads and the digital functions are not selected when the corresponding DACC
channels are enabled by writing to the DACC Channel Enable Register (DACC_CHER).
53.5.2 Power Management
The programmer must first enable the DACC Clock in the Power Management Controller (PMC) before using the
DACC.
The DACC becomes active as soon as a conversion is requested and at least one channel is enabled. The DACC is
automatically deactivated when no channels are enabled.
53.5.3 Interrupt Sources
The DACC interrupt line is connected on one of the internal sources of the Interrupt controller. Using the DACC
interrupt requires the Interrupt controller to be programmed first.
53.5.4 Conversion Performances
For performance and electrical characteristics of the DACC, see the DACC Characteristics in the section “Electrical
Characteristics”.
53.6 Functional Description
53.6.1 Digital-to-Analog Conversion
To perform conversions, the DACC_CHSR.CHx bit must be set by writing a one to DACC_CHER.CHx. If both
DACC_CHSR.CHx bits are cleared, the DAC analog cell is switched of
f. The DACx is ready to convert once
DACC_CHSR.DACRDYx is read at ‘1’.
The DACC divides the peripheral clock to perform conversions. This divided clock is named DAC clock. Once a
conversion starts, the DACC takes 12 DAC clock periods to provide the analog result on the selected analog output.
The minimum conversion period of the DAC is exactly 12 DAC clock periods when the Max speed mode is enabled
(MAXSx = 1 in the DACC Mode Register (DACC_MR)). In this case the DAC is always clocked, slightly increasing
the power consumption of the DAC.
When the Max speed mode is not used (Trigger or Free-running mode), the DAC is only clocked when a conversion
is requested and a new conversion can only occur when the DAC has ended its previous conversion. The power
consumption is lower but the sampling rate is lower as the controller waits for the end of conversion of the previously
sent data. In this case, one conversion lasts 12 DAC clock periods plus 2 cycles of resynchronization stage.
The conversion mode of a channel can be modified only if this channel has been previously disabled.
Power consumption of the DAC can be adapted to its sampling rate via the DACC_ACR.IBCTLCHx fields.
In Bypass mode, the maximum sample rate and the power consumption of the DAC are lowered.
53.6.2 Conversion Results
When a conversion is completed, the resulting analog value is available at the selected DAC channel output. The
EOC bit in the DACC Interrupt Status Register
(DACC_ISR) is set.
Reading DACC_ISR clears the EOC bit.
53.6.3 Analog Output Mode Selection
The analog outputs can be set to either Single-ended or Differential mode with the DIFF bit in the DACC_MR.
SAM E70/S70/V70/V71 Family
Digital-to-Analog Converter Controller (DACC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1707