Datasheet

53.3 Block Diagram
Figure 53-1. Block Diagram
DAC0/DACP
Analog Cell (DAC)
Digital-to-Analog Converter Controller (DACC)
Control
Logic
Interrupt
Controller
DMA
Peripheral Bridge
User
Interface
Trigger
Selection
DATRG
D
AC Core 0
DAC1/DACN
PMC
peripheral clock
Event System
Trigger
Selection
DAC Clock
DAC Core 1
VREFP
VDDANA
53.4 Signal Description
Table 53-1. DACC Signal Description
Name Description Direction
DAC0/DACP Single-ended analog output channel
0 / Positive channel of dif
ferential
analog output channel
Output
DAC1/DACN Single-ended analog output channel
1 / Negative channel of differential
analog output channel
Output
DATRG Trigger Input
VREFP Positive reference voltage connected
to VREFP
Input
VREFN Negative reference voltage
connected to VREFN
Input
SAM E70/S70/V70/V71 Family
Digital-to-Analog Converter Controller (DACC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1706