Datasheet

52.7.27 AFEC Channel Error Correction Register
Name: AFEC_CECR
Offset: 0xD8
Reset: 0x00000000
Property: Read/Write
This register can only be written if the WPEN bit is cleared in the AFEC W
rite Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
ECORR11 ECORR10 ECORR9 ECORR8
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ECORR7 ECORR6 ECORR5 ECORR4 ECORR3 ECORR2 ECORR1 ECORR0
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – ECORRx Error Correction Enable for Channel x
Value Description
0
Automatic error correction is disabled for channel x.
1
Automatic error correction is enabled for channel x.
SAM E70/S70/V70/V71 Family
Analog Front-End Controller (AFEC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1702