Datasheet

52.7.25 AFEC Correction Select Register
Name: AFEC_COSR
Offset: 0xD0
Reset: 0x00000000
Property: Read/Write
This register can only be written if the WPEN bit is cleared in the AFEC W
rite Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
CSEL
Access
R/W
Reset 0
Bit 0 – CSEL Sample & Hold unit
Correction Select
Selects the Sample & Hold unit to be displayed in the AFEC_CVR.
SAM E70/S70/V70/V71 Family
Analog Front-End Controller (AFEC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1700