Datasheet

52.7.24 AFEC Sample & Hold Mode Register
Name: AFEC_SHMR
Offset: 0xA0
Reset: 0x00000000
Property: Read/Write
This register can only be written if the WPEN bit is cleared in the AFEC W
rite Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
DUAL11 DUAL10 DUAL9 DUAL8
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DUAL7 DUAL6 DUAL5 DUAL4 DUAL3 DUAL2 DUAL1 DUAL0
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – DUALx Dual Sample & Hold for Channel x
Value Description
0
Single Sample-and-Hold mode.
1
Dual Sample-and-Hold mode.
SAM E70/S70/V70/V71 Family
Analog Front-End Controller (AFEC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1699