Datasheet

52.7.20 AFEC Channel Offset Compensation Register
Name: AFEC_COCR
Offset: 0x6C
Reset: 0x00000000
Property: Read/Write
This register can only be written if the WPEN bit is cleared in the AFEC W
rite Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
AOFF[9:8]
Access
R/W R/W
Reset 0 0
Bit 7 6 5 4 3 2 1 0
AOFF[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 9:0 – AOFF[9:0] Analog Of
fset
Defines the analog offset to be used for channel CSEL (configured in the AFEC Channel Selection Register). This
value is used as an input value for the DAC included in the AFE.
Note:
The field AOFF must be configured to 512 (mid scale of the DAC) when there is no offset error to compensate. To
compensate for an offset error of n LSB (positive or negative), the field AOFF must be configured to 512 + n.
SAM E70/S70/V70/V71 Family
Analog Front-End Controller (AFEC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1695