Datasheet

52.7.18 AFEC Channel Selection Register
Name: AFEC_CSELR
Offset: 0x64
Reset: 0x00000000
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
CSEL[3:0]
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bits 3:0 – CSEL[3:0] Channel Selection
Value Description
0–11
Selects the channel to be displayed in AFEC_CDR and AFEC_COCR. To be configured with the
appropriate channel number
.
SAM E70/S70/V70/V71 Family
Analog Front-End Controller (AFEC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1693