Datasheet

52.7.15 AFEC Compare Window Register
Name: AFEC_CWR
Offset: 0x50
Reset: 0x00000000
Property: Read/Write
This register can only be written if the WPEN bit is cleared in the AFEC W
rite Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
HIGHTHRES[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
HIGHTHRES[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
LOWTHRES[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
LOWTHRES[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 31:16 – HIGHTHRES[15:0] High Threshold
High threshold associated to compare settings of AFEC_EMR. For comparisons lower than 16 bits and signed, the
sign should be extended up to the bit 15.
Bits 15:0 – LOWTHRES[15:0] Low Threshold
Low threshold associated to compare settings of AFEC_EMR. For comparisons lower than 16 bits and signed, the
sign should be extended up to the bit 15.
SAM E70/S70/V70/V71 Family
Analog Front-End Controller (AFEC)
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 1690