Datasheet

52.7.10 AFEC Interrupt Enable 1 Register
Name: AFEC_IER
Offset: 0x24
Reset: –
Property: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No ef
fect.
1: Enables the corresponding interrupt.
Bit 31 30 29 28 27 26 25 24
TEMPCHG COMPE GOVRE DRDY
Access
W W W W
Reset – – – –
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
EOC11 EOC10 EOC9 EOC8
Access
W W W W
Reset – – – –
Bit 7 6 5 4 3 2 1 0
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
Access
W W W W W W W W
Reset – – – – – – – –
Bit 30 – TEMPCHG T
emperature Change Interrupt Enable
Bit 26 – COMPE Comparison Event Interrupt Enable
Bit 25 – GOVRE General Overrun Error Interrupt Enable
Bit 24 – DRDY Data Ready Interrupt Enable
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – EOCx End of Conversion Interrupt Enable x
SAM E70/S70/V70/V71 Family
Analog Front-End Controller (AFEC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1685