Datasheet

52.7.6 AFEC Channel Enable Register
Name: AFEC_CHER
Offset: 0x14
Reset: –
Property: Write-only
This register can only be written if the WPEN bit is cleared in the AFEC W
rite Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
CH11 CH10 CH9 CH8
Access
W W W W
Reset – – – –
Bit 7 6 5 4 3 2 1 0
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
Access
W W W W W W W W
Reset – – – – – – – –
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – CHx Channel x Enable
If AFEC_MR.USEQ = 1, CHx corresponds to the xth channel of the sequence described in AFEC_SEQ1R,
AFEC_SEQ2R.
Value Description
0
No effect.
1
Enables the corresponding channel.
SAM E70/S70/V70/V71 Family
Analog Front-End Controller (AFEC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1681