Datasheet

52.7.5 AFEC Channel Sequence 2 Register
Name: AFEC_SEQ2R
Offset: 0x10
Reset: 0x00000000
Property: Read/Write
This register can only be written if the WPEN bit is cleared in the AFEC W
rite Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
USCH11[3:0] USCH10[3:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
USCH9[3:0] USCH8[3:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 0:3, 4:7, 8:11, 12:15 – USCHx User Sequence Number x
The sequence number x (USCHx) can be programmed by the Channel number CHy where y is the value written in
this field. The allowed range is 0 up to
11. So it is only possible to use the sequencer from CH0 to CH11.
This register activates only if AFEC_MR.USEQ is set.
Any USCHx field is taken into account only if AFEC_CHSR.CHx is written to one, else any value written in USCHx
does not add the corresponding channel in the conversion sequence.
Configuring the same value in different fields leads to multiple samples of the same channel during the conversion
sequence. This can be done consecutively, or not, depending on user requirements.
SAM E70/S70/V70/V71 Family
Analog Front-End Controller (AFEC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1680