Datasheet

23.5.2 Supply Controller Supply Monitor Mode Register
Name: SUPC_SMMR
Offset: 0x04
Reset: 0x00000000
Property: Read/Write
This register is located in the VDDIO domain.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
SMIEN SMRSTEN SMSMPL[2:0]
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SMTH[3:0]
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 13 – SMIEN Supply Monitor Interrupt Enable
Value Description
0
(NOT_ENABLE): The SUPC interrupt signal is not affected when a supply monitor detection occurs.
1
(ENABLE): The SUPC interrupt signal is asserted when a supply monitor detection occurs.
Bit 12 – SMRSTEN Supply Monitor Reset Enable
Value Description
0
(NOT_ENABLE): The core reset signal vddcore_nreset is not affected when a supply monitor detection
occurs.
1
(ENABLE): The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs.
Bits 10:8 – SMSMPL[2:0] Supply Monitor Sampling Period
Value Name Description
0x0
SMD Supply Monitor disabled
0x1
CSM Continuous Supply Monitor
0x2
32SLCK Supply Monitor enabled one SLCK period every 32 SLCK periods
0x3
256SLCK Supply Monitor enabled one SLCK period every 256 SLCK periods
0x4
2048SLCK Supply Monitor enabled one SLCK period every 2,048 SLCK periods
Bits 3:0 – SMTH[3:0] Supply Monitor Threshold
Selects the threshold voltage of the supply monitor
. Refer to the section “Electrical Characteristics” for voltage values.
Related Links
58. Electrical Characteristics for SAM V70/V71
SAM E70/S70/V70/V71 Family
Supply Controller (SUPC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 167