Datasheet

• Gs—the value 15
CorrectedData = ConvertedData+OFFSETCORR ×
GAINCORR
2
Gs
Figure 52-14. AFE Digital Signal Processing
V
INN
AFE Average
Calibra
tion
Sign Mode AFE_LCDR
RES
GAINCORR
O
FFSETCORR
ADC_EMR
ADC_CVR
12-bit
2’
s complement
data format
12- to 16-bit
2’s complement
data format
12- to 16-bit
2’s complement
data format
12- to 16-bit
signed or unsigned
data
V
INP
52.6.16 Buffer Structure
The DMA read channel is triggered each time a new data is stored in AFEC_LCDR. The same structure of data is
repeatedly stored in AFEC_LCDR each time a trigger event occurs. Depending on the user mode of operation
(AFEC_MR, AFEC_CHSR, AFEC_SEQ1R, AFEC_SEQ2R) the structure dif
fers. When TAG is cleared, each data
transferred to DMA buffer is carried on a half-word (16-bit) and consists of the last converted data right-aligned.
When TAG is set, this data is carried on a word buffer (32-bit) and CHNB carries the channel number, thus simplifying
post-processing in the DMA buffer and ensuring the integrity of the DMA buffer.
52.6.17 Fault Output
The AFEC internal fault output is directly connected to the PWM fault input. Fault output may be asserted depending
on the configuration of AFEC_EMR, AFEC_CWR, AFEC_TEMPMR and AFEC_TEMPCWR and converted values.
T
wo types of comparison can trigger a compare event (fault output pulse). The first comparison type is based on
AFEC_CWR settings, thus on all converted channels except the last one; the second type is linked to the last
channel where temperature is measured. As an example, overcurrent and temperature exceeding limits can trigger a
fault to PWM.
When the compare occurs, the AFEC fault output generates a pulse of one peripheral clock cycle to the PWM fault
input. This fault line can be enabled or disabled within the PWM. If it is activated and asserted by the AFEC, the
PWM outputs are immediately placed in a safe state (pure combinational path).
Note that the AFEC fault output connected to the PWM is not the COMPE bit. Thus the Fault Mode (FMOD) within
the PWM configuration must be FMOD = 1.
52.6.18 Register Write Protection
To prevent any single software error from corrupting AFEC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the AFEC W
rite Protection Mode Register (AFEC_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the AFEC Write Protection Status
Register (AFEC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been
attempted.
The WPVS flag is automatically cleared by reading the AFEC_WPSR.
The protected registers are:
• AFEC Mode Register
• AFEC Extended Mode Register
• AFEC Channel Sequence 1 Register
• AFEC Channel Sequence 2 Register
• AFEC Channel Enable Register
• AFEC Channel Disable Register
SAM E70/S70/V70/V71 Family
Analog Front-End Controller (AFEC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1669