Datasheet

The channel of the temperature sensor is periodically converted together with the other enabled channels and the
result is placed into AFEC_LCDR and an internal register (can be read in AFEC_CDR). Thus the temperature
conversion result is part of the Peripheral DMA Controller buf
fer. The temperature channel can be enabled/disabled
at any time, but this may not be optimal for downstream processing.
Figure 52-8. Non-Optimized Temperature Conversion
Base Address (BA)
BA + 0x02
AFEC_CDR[TEMP]0
AFEC_CDR[0]0
AFEC_CDR[0]0
BA + 0x04
AFEC_CDR[0]0
AFEC_CDR[TEMP]0
AFEC_CDR[TEMP]0
BA + 0x06
BA + 0x08
BA + 0x0A
Assuming AFEC_CHSR[0] = 1 and AFEC_CHSR[TEMP] = 1
w
here TEMP is the index of the temperature sensor channel
trig.event1
DMA
Buffer
Structure
trig.event2
DMA Transfer
trig.event3
Internal/External
Trigger event
AFEC_SEL
C
T
C
T
T
C
T
C
C: Classic AFE Conversion Sequence - T: Temperature Sensor Channel
C
T
AFEC_CHSR[TEMP] = 1, AFEC_MR.TRGEN = 1 and AFEC_TEMPMR.RTCT = 0
AFEC_CDR[TEMP]
T1
T2T0
AFEC_CDR[0]
C0
C1
C2 C3
C4
C5
T3 T4
T5
AFEC_LCDR
C0
C1
C2 C3
C4
T1
T2T0
T3 T4 T5
The temperature factor has a slow variation rate and may be different from other conversion channels. As a result,
the AFEC allows a dif
ferent way of triggering temperature measurement when AFEC_TEMPMR.RTCT is set but
AFEC_CHSR.CH11 is cleared.
In this configuration, the measurement is triggered every second by means of an internal trigger generated by the
RTC. This trigger is always enabled and independent of the triggers used for other channels. In this mode of
operation, the temperature sensor is only powered for a period of time covering startup time and conversion time.
Every second, a conversion is scheduled for channel 11 but the result of the conversion is only uploaded to an
internal register read by means of AFEC_CDR, and not to AFEC_LCDR. Therefore, the temperature channel is not
part of the Peripheral DMA Controller buffer; only the enabled channel are kept in the buffer. The end of conversion of
the temperature channel is reported by means of the EOC11 flag in AFEC_ISR.
SAM E70/S70/V70/V71 Family
Analog Front-End Controller (AFEC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1664