Datasheet

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Single-Ended Input Pins Differential Input Pins Channel Numbers
AFE_AD1 & AFE_AD7 – CH1
... ... ...
AFE_AD4 & AFE_AD10 AFE_AD4–AFE_AD5 & AFE_AD10–AFE_AD11 CH4
AFE_AD5 & AFE_AD11 – CH5
Table 52-4. Input Pins and Channel Numbers in Single Sample-and-Hold Mode
Single-Ended Input Pins Differential Input Pins Channel Numbers
AFE_AD0 AFE_AD0-AFE_AD1 CH0
AFE_AD1 – CH1
... ... ...
AFE_AD10 AFE_AD10–AFE_AD11 CH10
AFE_AD11 – CH11
52.6.11 Input Gain and Offset
The AFE has a built-in programmable gain amplifier (PGA) and programmable offset per channel through a DAC.
The programmable gain amplifier can be set to gains of 1, 2 and 4 and can be used for single-ended applications or
for fully dif
ferential applications.
The AFEC can apply different gain and offset on each channel.
The gain is configured in the GAIN field of the Channel Gain Register (AFEC_CGR) as shown in the following table.
Table 52-5. Gain of the Sample-and-Hold Unit
GAIN GAIN (DIFFx = 0) GAIN (DIFFx = 1)
0 1 1
1 2 2
2 4 4
3 4 4
The analog offset of the AFE is configured in the AOFF field in the Channel Offset Compensation register
(AFEC_COCR). The of
fset is only available in Single-ended mode. The field AOFF must be configured to 512 (mid
scale of the DAC) when there is no offset error to compensate.To compensate for an offset error of n LSB (positive or
negative), the field AOFF must be configured to 512 + n.
SAM E70/S70/V70/V71 Family
Analog Front-End Controller (AFEC)
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 1662