Datasheet

52.6.6 Conversion Triggers
Conversions of the active analog channels are started with a software or hardware trigger. The software trigger is
provided by writing a ‘1’ to the bit ST
ART in the Control Register (AFEC_CR).
The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, PWM Event line, or the external
trigger input of the AFEC (ADTRG). The hardware trigger is selected with AFEC_MR.TRGSEL. The selected
hardware trigger is enabled with AFEC_MR.TRGEN
The minimum time between two consecutive trigger events must be strictly greater than the duration of the longest
conversion sequence according to configuration of registers AFEC_MR, AFEC_CHSR, AFEC_SEQ1R,
AFEC_SEQ2R.
If a hardware trigger is selected, the start of a conversion is triggered after a delay starting at each rising edge of the
selected signal. Due to asynchronous handling, the delay may vary in a range of two peripheral clock periods to one
AFE clock period. This delay varies from trigger to trigger and so introduces a jitter error leading to a reduced Signal-
to-Noise ratio performance.
Figure 52-6. Conversion Start with the Hardware Trigger
trigger
start
delay
If one of the TIOA outputs is selected, the corresponding Timer Counter channel must be programmed in Waveform
mode.
Only one start command is necessary to initiate a conversion sequence on all the channels. The AFEC hardware
logic automatically performs the conversions on the active channels, then waits for a new request. The Channel
Enable (AFEC_CHER) and Channel Disable (AFEC_CHDR) registers permit the analog channels to be enabled or
disabled independently
.
If the AFEC is used with a DMA, only the transfers of converted data from enabled channels are performed and the
resulting data buffers should be interpreted accordingly.
52.6.7 Sleep Mode and Conversion Sequencer
The AFEC Sleep mode maximizes power saving by automatically deactivating the AFE when it is not being used for
conversions. Sleep mode is selected by setting AFEC_MR.SLEEP
.
Sleep mode is managed by a conversion sequencer, which automatically processes the conversions of all channels
at lowest power consumption.
This mode can be used when the minimum period of time between two successive trigger events is greater than the
startup period of the AFEC. Refer to the AFE Characteristics in the section “Electrical Characteristics”.
When a start conversion request occurs, the AFE is automatically activated. As the analog cell requires a startup
time, the logic waits during this lapse and starts the conversion on the enabled channels. When all conversions are
complete, the AFE is deactivated until the next trigger. Triggers occurring during the sequence are not taken into
account.
A fast wakeup mode is available in the AFEC_MR as a compromise between power-saving strategy and
responsiveness. Setting the FWUP bit enables the Fast Wakeup mode. In Fast Wakeup mode, the AFE is not fully
deactivated while no conversion is requested, thereby providing lower power savings but faster wakeup.
The conversion sequencer allows automatic processing with minimum processor intervention and optimized power
consumption. Conversion sequences are performed periodically using a Timer/Counter output or the PWM event line.
The DMA can automatically process the periodic acquisition of several samples without processor intervention.
The sequence can be customized by programming the Channel Sequence registers AFEC_SEQ1R and
AFEC_SEQ2R and setting AFEC_MR.USEQ. The user selects a specific order of channels and can program up to
12 conversions by sequence. The user may create a personal sequence by writing channel numbers in
AFEC_SEQ1R and AFEC_SEQ2R. Channel numbers can be written in any order and repeated several times. Only
enabled USCHx fields are converted. Thus, to program a 15-conversion sequence, the user disables
AFEC_CHSR.CH15, thus disabling AFEC_SEQ2R.USCH15.
SAM E70/S70/V70/V71 Family
Analog Front-End Controller (AFEC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1660