Datasheet

• Standby Mode for Fast Wakeup Time Response
–
Powerdown capability
• Automatic Window Comparison of Converted Values
• Register Write Protection
52.3 Block Diagram
Figure 52-1. Analog Front-End Controller Block Diagram
AFE_ADTRG
VDDANA
VREFN
GND
Trigger
Selection
Timer
Counter
Channels
User
Interface
Interrupt
Controller
Analog Inputs
Multiplexed
with I/O lines
AFE Controller (AFEC)
AFE Analog Cell
CHx
10-bit
DA
Converter
AOFFx
AFEC Interrupt
en.
Analog
Mux
n/2->1
CHENx
Sample
a
nd Hold
PGA0
Prog. Gain
Amplifier
Digital
Averaging
with OSR
GAINx
RES
AFE_AD0
AFE_AD1
AFE_ADn-1
AFE_AD(n/2-1)
AFE_AD(n/2)
S&H
+
-
S&H
+
-
Analog
Mux
2->1
PIO
Extra
Funct.
Channel
Sequencer
PGA1
Analog
Mux
n/2->1
Peripheral Bridge
APB
DMA
System Bus
Peripheral Clock
PMC
Bus Clock
AOFFx
VREFP
10-bit
DA
Converter
12-bit
AD
Converter
52.4 Signal Description
Table 52-1. AFEC Signal Description
Pin Name Description
VREFP Reference voltage
VREFN Reference voltage
AFE_AD0—AFE_AD11
(1)
Analog input channels
AFE_ADTRG External trigger
Note:
1.
AFE_AD11 is not an actual pin but is connected to a temperature sensor.
SAM E70/S70/V70/V71 Family
Analog Front-End Controller (AFEC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1654