Datasheet

52. Analog Front-End Controller (AFEC)
52.1 Description
The Analog Front-End Controller (AFEC) is based on an Analog Front-End (AFE) cell integrating a 12-bit Analog-to-
Digital Converter (ADC), a Programmable Gain Amplifier (PGA), a Digital-to-Analog Converter (DAC) and
two 6-to-1
analog multiplexers, making possible the analog-to-digital conversions of 12 analog lines (in single Sample-and-Hold
mode) or two simultaneous conversions of 6 analog lines (in dual Sample-and-Hold mode). The conversions extend
from 0V to VREFP. The AFEC supports a 12-bit resolution mode which can be extended up to a 16-bit resolution by
digital averaging.
Conversion results are reported in a common register for all channels, as well as in a channel-dedicated register.
Software trigger, external trigger on rising edge of the AFE_ADTRG pin or internal triggers from Timer Counter
output(s) are configurable.
The comparison circuitry allows automatic detection of values below a threshold, higher than a threshold, in a given
range or outside the range. Thresholds and ranges are fully configurable.
The AFEC internal fault output is directly connected to PWM Fault input. This input can be asserted by means of
comparison circuitry in order to immediately put the PWM outputs in a safe state (pure combinational path).
The AFEC also integrates a Sleep mode and a conversion sequencer and connects with a DMA channel. These
features reduce both power consumption and processor intervention.
The AFEC has a selectable single-ended or fully differential input and benefits from a 2-bit programmable gain. A set
of reference voltages is generated internally from a single external reference voltage node that may be equal to the
analog supply voltage. An external decoupling capacitance is required for noise filtering.
A digital error correction circuit based on the multi-bit redundant signed digit (RSD) algorithm is employed in order to
reduce INL and DNL errors.
Finally, the user can configure AFE timings, such as startup time and tracking time.
52.2 Embedded Characteristics
• 12-bit Resolution up to 16-bit Resolution by Digital Averaging
• Wide Range of Power Supply Operation
• Selectable Single-ended or Differential Input Voltage
• Selectable Single or Dual Sample-and-Hold Mode
• Programmable Gain for Maximum Full-Scale Input Range 0–V
DD
• Programmable Offset Per Channel
• Automatic Correction of Offset and Gain Errors
• Integrated Multiplexers Offering Up to 12 Independent Analog Inputs
• Individual Enable and Disable of Each Channel
• Hardware or Software Trigger
– External trigger pin
– Timer counter outputs (corresponding TIOA trigger)
– PWM event line
• Drive of PWM Fault Input
• DMA Support
• Possibility of AFE Timings Configuration
• Two Sleep Modes and Conversion Sequencer
– Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels
– Possibility of customized channel sequence
SAM E70/S70/V70/V71 Family
Analog Front-End Controller (AFEC)
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 1653