Datasheet

51.7.47 PWM Channel Dead Time Update Register
Name: PWM_DTUPDx
Offset: 0x021C + x*0x20 [x=0..3]
Reset: 0x00000000
Property: Write-only
This register can only be written if bits WPSWS4 and WPHWS4 are cleared in the PWM W
rite Protection Status
Register.
This register acts as a double buffer for the DTH and DTL values. This prevents an unexpected waveform when
modifying the dead-time values.
Only the first 12 bits (dead-time counter size) of fields DTHUPD and DTLUPD are significant.
Bit 31 30 29 28 27 26 25 24
DTLUPD[15:8]
Access
W W W W W W W W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
DTLUPD[7:0]
Access
W W W W W W W W
Reset 0 0 0 0 0 0 0 –
Bit 15 14 13 12 11 10 9 8
DTHUPD[15:8]
Access
W W W W W W W W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DTHUPD[7:0]
Access
W W W W W W W W
Reset 0 0 0 0 0 0 0 –
Bits 31:16 – DTLUPD[15:0] Dead-T
ime Value Update for PWMLx Output
Defines the dead-time value for PWMLx output. This value must be defined between 0 and CDTY (PWM_CDTYx).
This value is applied only at the beginning of the next channel x PWM period.
Bits 15:0 – DTHUPD[15:0] Dead-Time Value Update for PWMHx Output
Defines the dead-time value for PWMHx output. This value must be defined between 0 and the value (CPRD –
CDTY) (PWM_CPRDx and PWM_CDTYx). This value is applied only at the beginning of the next channel x PWM
period.
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1648