Datasheet

51.7.43 PWM Channel Period Register
Name: PWM_CPRDx
Offset: 0x020C + x*0x20 [x=0..3]
Reset: 0x00000000
Property: Read/Write
This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the PWM W
rite Protection Status
Register.
Only the first 16 bits (channel counter size) are significant.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
CPRD[23:16]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
CPRD[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CPRD[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 23:0 – CPRD[23:0] Channel Period
If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and
can be calculated:
– By using the PWM peripheral clock divided by a given prescaler value “X” (where X = 2
PREA
is 1, 2, 4, 8, 16, 32, 64,
128, 256, 512, or 1024). The resulting period formula is:
 × CPRD

peripheralclock
– By using the PWM peripheral clock divided by a given prescaler value “X” (see above) and by either the DIVA or
the DIVB divider
. The formula becomes, respectively:
 ×
CPRD × DIVA

peripheralclock
or
 ×
CPRD × DIVB

peripheralclock
If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and
can be calculated:
– By using the PWM peripheral clock divided by a given prescaler value “X” (where X = 2
PREA
is 1, 2, 4, 8, 16, 32, 64,
128, 256, 512, or 1024). The resulting period formula is:
2 ×  ×
CPRD

peripheralclock
– By using the PWM peripheral clock divided by a given prescaler value “X” (see above) and by either the DIVA or
the DIVB divider
. The formula becomes, respectively:
2 ×  ×
CPRD × DIVA

peripheralclock
or
2 ×  ×
CPRD × DIVB

peripheralclock
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1643