Datasheet

Bit 12 – DPOLI Disabled Polarity Inverted
Value Description
0
When the PWM channel x is disabled (CHIDx(PWM_SR) = 0), the OCx output waveform is the same
as the one defined by the CPOL bit.
1
When the PWM channel x is disabled (CHIDx(PWM_SR) = 0), the OCx output waveform is inverted
compared to the one defined by the CPOL bit.
Bit 11 – UPDS Update Selection
If the PWM period is center-aligned (CALG=1):
0: The update occurs at the next end of the PWM period after writing the update register(s).
1: The update occurs at the next end of the PWM half period after writing the update register(s).
If the PWM period is left-aligned (CALG=0), the update always occurs at the end of the PWM period after writing the
update register(s).
Bit 10 – CES Counter Event Selection
The bit CES defines when the channel counter event occurs when the period is center-aligned (flag CHIDx in PWM
Interrupt Status Register 1).
If the PWM period is center-aligned (CALG=1):
0: The channel counter event occurs at the end of the PWM period.
1: The channel counter event occurs at the end of the PWM period and at half the PWM period.
If the PWM period is left-aligned (CALG=0), the channel counter event occurs at the end of the period and the CES
bit has no ef
fect.
Bit 9 – CPOL Channel Polarity
Value Description
0
The OCx output waveform (output from the comparator) starts at a low level.
1
The OCx output waveform (output from the comparator) starts at a high level.
Bit 8 – CALG Channel Alignment
Value Description
0
The period is left-aligned.
1
The period is center-aligned.
Bits 3:0 – CPRE[3:0] Channel Prescaler
Value Name Description
MCK Peripheral clock
1
MCK_DIV_2 Peripheral clock/2
2
MCK_DIV_4 Peripheral clock/4
3
MCK_DIV_8 Peripheral clock/8
4
MCK_DIV_16 Peripheral clock/16
5
MCK_DIV_32 Peripheral clock/32
6
MCK_DIV_64 Peripheral clock/64
7
MCK_DIV_128 Peripheral clock/128
8
MCK_DIV_256 Peripheral clock/256
9
MCK_DIV_512 Peripheral clock/512
10
MCK_DIV_1024 Peripheral clock/1024
11
CLKA Clock A
12
CLKB Clock B
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1640