Datasheet

51.7.30 PWM Spread Spectrum Register
Name: PWM_SSPR
Offset: 0xA0
Reset: 0x00000000
Property: Read/Write
This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the PWM W
rite Protection Status
Register.
Only the first 16 bits (channel counter size) are significant.
Bit 31 30 29 28 27 26 25 24
SPRDM
Access
R/W
Reset 0
Bit 23 22 21 20 19 18 17 16
SPRD[23:16]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
SPRD[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SPRD[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 24 – SPRDM Spread Spectrum Counter Mode
Value Description
0
Triangular mode. The spread spectrum counter starts to count from -SPRD when the channel 0 is
enabled and counts upwards at each PWM period. When it reaches +SPRD, it restarts to count from -
SPRD again.
1
Random mode. The spread spectrum counter is loaded with a new random value at each PWM period.
This random value is uniformly distributed and is between -SPRD and +SPRD.
Bits 23:0 – SPRD[23:0] Spread Spectrum Limit V
alue
The spread spectrum limit value defines the range for the spread spectrum counter. It is introduced in order to
achieve constant varying PWM period for the output waveform.
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1629