Datasheet

51.7.27 PWM Fault Protection Value Register 1
Name: PWM_FPV1
Offset: 0x68
Reset: 0x00000000
Property: Read/Write
This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the PWM W
rite Protection Status
Register.
See Fault Inputs for details on fault generation.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
FPVL3 FPVL2 FPVL1 FPVL0
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
FPVH3 FPVH2 FPVH1 FPVH0
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bits 16, 17, 18, 19 – FPVLx Fault Protection V
alue for PWML output on channel x
This bit is taken into account only if the bit FPZLx is set to ‘0’ in PWM Fault Protection Value Register 2.
Value Description
0
PWML output of channel x is forced to ‘0’ when fault occurs.
1
PWML output of channel x is forced to ‘1’ when fault occurs.
Bits 0, 1, 2, 3 – FPVHx Fault Protection V
alue for PWMH output on channel x
This bit is taken into account only if the bit FPZHx is set to ‘0’ in PWM Fault Protection Value Register 2.
Value Description
0
PWMH output of channel x is forced to ‘0’ when fault occurs.
1
PWMH output of channel x is forced to ‘1’ when fault occurs.
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1626