Datasheet

51.7.24 PWM Fault Mode Register
Name: PWM_FMR
Offset: 0x5C
Reset: 0x00000000
Property: Read/Write
This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the PWM W
rite Protection Status
Register.
See Fault Inputs for details on fault generation.
CAUTION
To prevent an unexpected activation of the status flag FSy in the PWM Fault Status Register, the bit
FMODy can be set to ‘1’ only if the FPOL
y bit has been previously configured to its final value.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
FFIL[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
FMOD[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
FPOL[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 23:16 – FFIL[7:0] Fault Filtering
For each bit y of FFIL, where y is the fault input number:
0: The fault input y is not filtered.
1: The fault input y is filtered.
Bits 15:8 – FMOD[7:0] Fault Activation Mode
For each bit y of FMOD, where y is the fault input number:
0: The fault y is active until the fault condition is removed at the peripheral
(1)
level.
1: The fault y stays active until the fault condition is removed at the peripheral level
(1)
AND until it is cleared in the
PWM Fault Clear Register.
Note:
1.
The peripheral generating the fault.
Bits 7:0 – FPOL[7:0] Fault Polarity
For each bit y of FPOL, where y is the fault input number:
0: The fault y becomes active when the fault input y is at 0.
1: The fault y becomes active when the fault input y is at 1.
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1623