Datasheet

51.7.16 PWM Interrupt Mask Register 2
Name: PWM_IMR2
Offset: 0x3C
Reset: 0x00000000
Property: Read-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
UNRE WRDY
Access
R R
Reset 0 0
Bits 16, 17, 18, 19, 20, 21, 22, 23 – CMPUx Comparison x Update Interrupt Mask
Bits 8, 9, 10, 1
1, 12, 13, 14, 15 – CMPMx Comparison x Match Interrupt Mask
Bit 3 – UNRE Synchronous Channels Update Underrun Error Interrupt Mask
Bit 0 – WRDY Write Ready for Synchronous Channels Update Interrupt Mask
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1615