Datasheet

51.7.15 PWM Interrupt Disable Register 2
Name: PWM_IDR2
Offset: 0x38
Reset: –
Property: Write-only
This register can only be written if bits WPSWS1 and WPHWS1 are cleared in the PWM W
rite Protection Status
Register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0
Access
W W W W W W W W
Reset 0 0 0 0 0 0 0 –
Bit 15 14 13 12 11 10 9 8
CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0
Access
W W W W W W W W
Reset 0 0 0 0 0 0 0 –
Bit 7 6 5 4 3 2 1 0
UNRE WRDY
Access
W W
Reset – –
Bits 16, 17, 18, 19, 20, 21, 22, 23 – CMPUx Comparison x Update Interrupt Disable
Bits 8, 9, 10, 1
1, 12, 13, 14, 15 – CMPMx Comparison x Match Interrupt Disable
Bit 3 – UNRE Synchronous Channels Update Underrun Error Interrupt Disable
Bit 0 – WRDY Write Ready for Synchronous Channels Update Interrupt Disable
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1614