Datasheet

51.7.13 PWM Sync Channels Update Period Update Register
Name: PWM_SCUPUPD
Offset: 0x30
Reset: –
Property: Write-only
This register acts as a double buffer for the UPR value. This prevents an unexpected automatic trigger of the update
of synchronous channels.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
UPRUPD[3:0]
Access
W W W W
Reset 0 0 0 –
Bits 3:0 – UPRUPD[3:0] Update Period Update
Defines the wanted time between each update of the synchronous channels if automatic trigger of the update is
activated (UPDM = 1 or UPDM = 2 in PWM Sync Channels Mode Register). This time is equal to UPR+1 periods of
the synchronous channels.
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1612