Datasheet

51.7.12 PWM Sync Channels Update Period Register
Name: PWM_SCUP
Offset: 0x2C
Reset: 0x00000000
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
UPRCNT[3:0] UPR[3:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 7:4 – UPRCNT[3:0] Update Period Counter
Reports the value of the update period counter
.
Bits 3:0 – UPR[3:0] Update Period
Defines the time between each update of the synchronous channels if automatic trigger of the update is activated
(UPDM = 1 or UPDM = 2 in PWM Sync Channels Mode Register). This time is equal to UPR+1 periods of the
synchronous channels.
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
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2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 1611