Datasheet

51.7.11 PWM Sync Channels Update Control Register
Name: PWM_SCUC
Offset: 0x28
Reset: 0x00000000
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
UPDULOCK
Access
R/W
Reset 0
Bit 0 – UPDULOCK Synchronous Channels Update Unlock
This bit is automatically reset when the update is done.
Value Description
0
No effect
1
If the UPDM field is set to ‘0’ in PWM Sync Channels Mode Register, writing the UPDULOCK bit to ‘1’
triggers the update of the period value, the duty-cycle and the dead-time values of synchronous
channels at the beginning of the next PWM period. If the field UPDM is set to ‘1’ or ‘2’, writing the
UPDULOCK bit to ‘1’ triggers only the update of the period value and of the dead-time values of
synchronous channels.
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1610