Datasheet

51.7.10 PWM DMA Register
Name: PWM_DMAR
Offset: 0x24
Reset: –
Property: Write-only
Only the first 16 bits (channel counter size) are significant.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
DMADUTY[23:16]
Access
W W W W W W W W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DMADUTY[15:8]
Access
W W W W W W W W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
DMADUTY[7:0]
Access
W W W W W W W W
Reset 0 0 0 0 0 0 0 –
Bits 23:0 – DMADUTY[23:0] Duty-Cycle Holding Register for DMA Access
Each write access to PWM_DMAR sequentially updates PWM_CDTYUPDx.CDTYUPD with DMADUTY (only for
channel configured as synchronous). See “Method 3: Automatic write of duty-cycle values and automatic trigger of
the update” .
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1609