Datasheet

51.7.9 PWM Sync Channels Mode Register
Name: PWM_SCM
Offset: 0x20
Reset: 0x00000000
Property: Read/Write
This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM W
rite Protection Status
Register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
PTRCS[2:0] PTRM UPDM[1:0]
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
SYNC3 SYNC2 SYNC1 SYNC0
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bits 23:21 – PTRCS[2:0] DMA Controller T
ransfer Request Comparison Selection
Selection of the comparison used to set the flag WRDY and the corresponding DMA Controller transfer request.
Bit 20 – PTRM DMA Controller Transfer Request Mode
UPDM PTRM WRDY Flag and DMA Controller Transfer Request
0 x The WRDY flag in PWM Interrupt Status Register 2
and the DMA transfer request are never set to
‘1’.
1 x The WRDY flag in PWM Interrupt Status Register 2 is set to ‘1’ as soon as the update period is
elapsed, the DMA Controller transfer request is never set to ‘1’.
2 0 The WRDY flag in PWM Interrupt Status Register 2 and the DMA transfer request are set to ‘1’ as
soon as the update period is elapsed.
1 The WRDY flag in PWM Interrupt Status Register 2 and the DMA transfer request are set to ‘1’ as
soon as the selected comparison matches.
Bits 17:16 – UPDM[1:0] Synchronous Channels Update Mode
Value Name Description
0
MODE0 Manual write of double buffer registers and manual update of synchronous channels 1
(1)
.
1
MODE1 Manual write of double buffer registers and automatic update of synchronous channels 2
(2)
.
2
MODE2 The WRDY flag in PWM Interrupt Status Register 2
and the DMA transfer request are set to
‘1’ as soon as the update period is elapsed.
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1607