Datasheet

51.7.5 PWM Interrupt Enable Register 1
Name: PWM_IER1
Offset: 0x10
Reset: –
Property: Write-only
This register can only be written if bits WPSWS1 and WPHWS1 are cleared in the PWM W
rite Protection Status
Register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
FCHID3 FCHID2 FCHID1 FCHID0
Access
W W W W
Reset 0 0 0 –
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
CHID3 CHID2 CHID1 CHID0
Access
W W W W
Reset 0 0 0 –
Bits 16, 17, 18, 19 – FCHIDx Fault Protection T
rigger on Channel x Interrupt Enable
Bits 0, 1, 2, 3 – CHIDx Counter Event on Channel x Interrupt Enable
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1603