Datasheet

51.7.4 PWM Status Register
Name: PWM_SR
Offset: 0x0C
Reset: 0x00000000
Property: Read-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
CHID3 CHID2 CHID1 CHID0
Access
R R R R
Reset 0 0 0 0
Bits 0, 1, 2, 3 – CHIDx Channel ID
Value Description
0
PWM output for channel x is disabled.
1
PWM output for channel x is enabled.
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1602