Datasheet

Value Name Description
3
CLK_DIV8 Peripheral clock/8
4
CLK_DIV16 Peripheral clock/16
5
CLK_DIV32 Peripheral clock/32
6
CLK_DIV64 Peripheral clock/64
7
CLK_DIV128 Peripheral clock/128
8
CLK_DIV256 Peripheral clock/256
9
CLK_DIV512 Peripheral clock/512
10
CLK_DIV1024 Peripheral clock/1024
Other
– Reserved
Bits 7:0 – DIVA[7:0] CLKA Divide Factor
Value Name Description
0
CLKA_POFF CLKA clock is turned off
1
PREA CLKA clock is clock selected by PREA
2–255
PREA_DIV CLKA clock is clock selected by PREA divided by DIVA factor
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1599