Datasheet

51.7 Register Summary
Offset Name Bit Pos.
0x00 PWM_CLK
7:0 DIVA[7:0]
15:8 PREA[3:0]
23:16 DIVB[7:0]
31:24 PREB[3:0]
0x04 PWM_ENA
7:0 CHID3 CHID2 CHID1 CHID0
15:8
23:16
31:24
0x08 PWM_DIS
7:0 CHID3 CHID2 CHID1 CHID0
15:8
23:16
31:24
0x0C PWM_SR
7:0 CHID3 CHID2 CHID1 CHID0
15:8
23:16
31:24
0x10 PWM_IER1
7:0 CHID3 CHID2 CHID1 CHID0
15:8
23:16 FCHID3 FCHID2 FCHID1 FCHID0
31:24
0x14 PWM_IDR1
7:0 CHID3 CHID2 CHID1 CHID0
15:8
23:16 FCHID3 FCHID2 FCHID1 FCHID0
31:24
0x18 PWM_IMR1
7:0 CHID3 CHID2 CHID1 CHID0
15:8
23:16 FCHID3 FCHID2 FCHID1 FCHID0
31:24
0x1C PWM_ISR1
7:0 CHID3 CHID2 CHID1 CHID0
15:8
23:16 FCHID3 FCHID2 FCHID1 FCHID0
31:24
0x20 PWM_SCM
7:0 SYNC3 SYNC2 SYNC1 SYNC0
15:8
23:16 PTRCS[2:0] PTRM UPDM[1:0]
31:24
0x24 PWM_DMAR
7:0 DMADUTY[7:0]
15:8 DMADUTY[15:8]
23:16 DMADUTY[23:16]
31:24
0x28 PWM_SCUC
7:0 UPDULOCK
15:8
23:16
31:24
0x2C PWM_SCUP
7:0 UPRCNT[3:0] UPR[3:0]
15:8
23:16
31:24
0x30 PWM_SCUPUPD
7:0 UPRUPD[3:0]
15:8
23:16
31:24
0x34 PWM_IER2
7:0 UNRE WRDY
15:8 CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0
23:16 CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0
31:24
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1589