Datasheet

Figure 51-33. Leading-Edge Blanking
PWMx Output
Waveform
x = [1,2]
TRGINx input
x = [1,2]
Blanking signal on TRGINx
x = [1,2]
Blanked trigger event x
x = [1,2]
Delay Delay Delay Delay
A
nalog Power
Signal
Switching Noise
51.6.6 PWM Controller Operations
51.6.6.1 Initialization
Before enabling the channels, they must be configured by the software application as described below:
•
Unlock User Interface by writing the WPCMD field in PWM_WPCR.
• Configuration of the clock generator (DIVA, PREA, DIVB, PREB in the PWM_CLK register if required).
• Selection of the clock for each channel (CPRE field in PWM_CMRx)
• Configuration of the waveform alignment for each channel (CALG field in PWM_CMRx)
• Selection of the counter event selection (if CALG = 1) for each channel (CES field in PWM_CMRx)
• Configuration of the output waveform polarity for each channel (CPOL bit in PWM_CMRx)
• Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in PWM_CPRDx
register is possible while the channel is disabled. After validation of the channel, the user must use
PWM_CPRDUPDx register to update PWM_CPRDx as explained below.
• Configuration of the duty-cycle for each channel (CDTY in the PWM_CDTYx register). Writing in PWM_CDTYx
register is possible while the channel is disabled. After validation of the channel, the user must use
PWM_CDTYUPDx register to update PWM_CDTYx as explained below.
• Configuration of the dead-time generator for each channel (DTH and DTL in PWM_DTx) if enabled (DTE bit in
PWM_CMRx). Writing in the PWM_DTx register is possible while the channel is disabled. After validation of the
channel, the user must use PWM_DTUPDx register to update PWM_DTx
• Selection of the synchronous channels (SYNCx in the PWM_SCM register)
• Selection of the moment when the WRDY flag and the corresponding DMA Controller transfer request are set
(PTRM and PTRCS in the PWM_SCM register)
• Configuration of the Update mode (UPDM in PWM_SCM register)
• Configuration of the update period (UPR in PWM_SCUP register) if needed
• Configuration of the comparisons (PWM_CMPVx and PWM_CMPMx)
• Configuration of the event lines (PWM_ELMRx)
• Configuration of the fault inputs polarity (FPOL in PWM_FMR)
• Configuration of the fault protection (FMOD and FFIL in PWM_FMR, PWM_FPV and PWM_FPE)
• Enable of the interrupts (writing CHIDx and FCHIDx in PWM_IER1, and writing WRDY, UNRE, CMPMx and
CMPUx in PWM_IER2)
• Enable of the PWM channels (writing CHIDx in the PWM_ENA register)
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1583