Datasheet

Figure 51-23. Comparison Unit Block Diagram
=
fault on channel 0
CNT [PWM_CCNT0]
CNT [PWM_CCNT0] is decrementing
CALG [PWM_CMR0]
CV [PWM_CMPVx]
=
1
0
1
Comparison x
CVM [PWM_CMPVx]
=
CPRCNT [PWM_CMPMx]
CTR [PWM_CMPMx]
CEN [PWM_CMPMx]
The comparison x matches when it is enabled by the bit CEN in the PWM Comparison x Mode Register
(PWM_CMPMx for the comparison x) and when the counter of the channel 0 reaches the comparison value defined
by the field CV in PWM Comparison x V
alue Register (PWM_CMPVx for the comparison x). If the counter of the
channel 0 is center-aligned (CALG = 1 in PWM Channel Mode Register), the bit CVM in PWM_CMPVx defines if the
comparison is made when the counter is counting up or counting down (in Left-alignment mode CALG = 0, this bit is
useless).
If a fault is active on the channel 0, the comparison is disabled and cannot match (see Fault Protection).
The user can define the periodicity of the comparison x by the fields CTR and CPR in PWM_CMPMx. The
comparison is performed periodically once every CPR+1 periods of the counter of the channel 0, when the value of
the comparison period counter CPRCNT in PWM_CMPMx reaches the value defined by CTR. CPR is the maximum
value of the comparison period counter CPRCNT. If CPR = CTR = 0, the comparison is performed at each period of
the counter of the channel 0.
The comparison x configuration can be modified while the channel 0 is enabled by using the PWM Comparison x
Mode Update Register (PWM_CMPMUPDx registers for the comparison x). In the same way, the comparison x value
can be modified while the channel 0 is enabled by using the PWM Comparison x Value Update Register
(PWM_CMPVUPDx registers for the comparison x).
The update of the comparison x configuration and the comparison x value is triggered periodically after the
comparison x update period. It is defined by the field CUPR in PWM_CMPMx. The comparison unit has an update
period counter independent from the period counter to trigger this update. When the value of the comparison update
period counter CUPRCNT (in PWM_CMPMx) reaches the value defined by CUPR, the update is triggered. The
comparison x update period CUPR itself can be updated while the channel 0 is enabled by using the
PWM_CMPMUPDx register.
CAUTION
The write of PWM_CMPVUPDx must be followed by a write of PWM_CMPMUPDx.
The comparison match and the comparison update can be source of an interrupt, but only if it is enabled and not
masked. These interrupts can be enabled by the PWM Interrupt Enable Register 2
and disabled by the PWM
Interrupt Disable Register 2. The comparison match interrupt and the comparison update interrupt are reset by
reading the PWM Interrupt Status Register 2.
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1574