Datasheet
Defining a channel as a synchronous channel while it is an asynchronous channel (by writing the bit SYNCx to ‘1’
while it was at ‘0’) is allowed only if the channel is disabled at this time (CHIDx = 0 in PWM_SR). In the same way
,
defining a channel as an asynchronous channel while it is a synchronous channel (by writing the SYNCx bit to ‘0’
while it was ‘1’) is allowed only if the channel is disabled at this time.
The UPDM field (Update Mode) in the PWM_SCM register selects one of the three methods to update the registers
of the synchronous channels:
• Method 1 (UPDM = 0): The period value, the duty-cycle values and the dead-time values must be written by the
processor in their respective update registers (respectively PWM_CPRDUPDx, PWM_CDTYUPDx and
PWM_DTUPDx).The update is triggered at the next PWM period as soon as the bit UPDULOCK in the PWM
Sync Channels Update Control Register (PWM_SCUC) is set to ‘1’.
• Method 2 (UPDM = 1): The period value, the duty-cycle values, the dead-time values and the update period
value must be written by the processor in their respective update registers (respectively PWM_CPRDUPDx,
PWM_CDTYUPDx and PWM_DTUPD). The update of the period value and of the dead-time values is triggered
at the next PWM period as soon as the bit UPDULOCK in the PWM_SCUC register is set to ‘1’. The update of
the duty-cycle values and the update period value is triggered automatically after an update period defined by
the field UPR in the PWM Sync Channels Update Period Register (PWM_SCUP).
• Method 3 (UPDM = 2): Same as Method 2 apart from the fact that the duty-cycle values of ALL synchronous
channels are written by the DMA Controller. The user can choose to synchronize the DMA Controller transfer
request with a comparison match (see Section 7.3 “PWM Comparison Units”), by the fields PTRM and PTRCS
in the PWM_SCM register. The DMA destination address must be configured to access only the PWM DMA
Register (PWM_DMAR). The DMA buffer data structure must consist of sequentially repeated duty cycles. The
number of duty cycles in each sequence corresponds to the number of synchronized channels. Duty cycles in
each sequence must be ordered from the lowest to the highest channel index. The size of the duty cycle is 16
bits.
Table 51-4. Summary of the Update of Registers of Synchronous Channels
Register UPDM = 0 UPDM = 1 UPDM = 2
Period Value
(PWM_CPRDUPDx)
Write by the processor
Update is triggered at the next PWM period as soon as the bit UPDULOCK is set to ‘1’
Dead-Time Values
(PWM_DTUPDx)
Write by the processor
Update is triggered at the next PWM period as soon as the bit UPDULOCK is set to ‘1’
Duty-Cycle Values
(PWM_CDTYUPDx)
Write by the processor Write by the processor Write by the DMA Controller
Update is triggered at the
next PWM period as soon
as the bit UPDULOCK is
set to ‘1’
Update is triggered at the next PWM period as soon as
the update period counter has reached the value UPR.
Update Period Value
(PWM_SCUPUPD)
Not applicable Write by the processor
Not applicable Update is triggered at the next PWM period as soon as
the update period counter has reached the value UPR.
51.6.2.9.1 Method 1: Manual write of duty-cycle values and manual trigger of the update
In this mode, the update of the period value, the duty-cycle values and the dead-time values must be done by writing
in their respective update registers with the processor (respectively PWM_CPRDUPDx, PWM_CDTYUPDx and
PWM_DTUPDx).
T
o trigger the update, the user must use the bit UPDULOCK in the PWM_SCUC register which allows to update
synchronously (at the same PWM period) the synchronous channels:
• If the bit UPDULOCK is set to ‘1’, the update is done at the next PWM period of the synchronous channels.
• If the UPDULOCK bit is not set to ‘1’, the update is locked and cannot be performed.
After writing the UPDULOCK bit to ‘1’, it is held at this value until the update occurs, then it is read 0.
Sequence for Method 1:
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1569