Datasheet

(PWM_FCR). In the PWM Fault Status Register (PWM_FSR), the field FIV indicates the current level of the fault
inputs and the field FIS indicates whether a fault is currently active.
Each fault can be taken into account or not by the fault protection mechanism in each channel. T
o be taken into
account in the channel x, the fault y must be enabled by the bit FPEx[y] in the PWM Fault Protection Enable register
(PWM_FPE1). However, synchronous channels (see Synchronous Channels) do not use their own fault enable bits,
but those of the channel 0 (bits FPE0[y]).
The fault protection on a channel is triggered when this channel is enabled and when any one of the faults that are
enabled for this channel is active. It can be triggered even if the PWM peripheral clock is not running but only by a
fault input that is not glitch-filtered.
When the fault protection is triggered on a channel, the fault protection mechanism resets the counter of this channel
and forces the channel outputs to the values defined by the fields FPVHx and FPVLx in the PWM Fault Protection
Value Register 1 (PWM_FPV) and fields FPZHx/FPZLx in the PWM Fault Protection Value Register 2, as shown in
the table below. The output forcing is made asynchronously to the channel counter.
Table 51-3. Forcing Values of PWM Outputs by Fault Protection
FPZH/Lx FPVH/Lx Forcing Value of PWMH/Lx
0 0 0
0 1 1
1 – High impedance state (Hi-Z)
CAUTION
• To prevent any unexpected activation of the status flag FSy in PWM_FSR, the FMODy bit can be set
to ‘1’ only if the FPOL
y bit has been previously configured to its final value.
• To prevent any unexpected activation of the Fault Protection on the channel x, the bit FPEx[y] can be
set to ‘1’ only if the FPOLy bit has been previously configured to its final value.
If a comparison unit is enabled (see PWM Comparison Units) and if a fault is triggered in the channel 0, then the
comparison cannot match.
As soon as the fault protection is triggered on a channel, an interrupt (dif
ferent from the interrupt generated at the end
of the PWM period) can be generated but only if it is enabled and not masked. The interrupt is reset by reading the
interrupt status register, even if the fault which has caused the trigger of the fault protection is kept active.
51.6.2.7.1 Recoverable Fault
The PWM provides a Recoverable Fault mode on fault 1 and 2 (see figure Fault Protection).
The recoverable fault signal is an internal signal generated as soon as an external trigger event occurs (see PWM
External T
rigger Mode).
When the fault 1 or 2 is defined as a recoverable fault, the corresponding fault input pin is ignored and bits FFIL1/2,
FMOD1/2 and FFIL1/2 are not taken into account.
The fault 1 is managed as a recoverable fault by the PWMEXTRG1 input trigger when PWM_ETRG1.RFEN = 1,
PWM_ENA.CHID1 = 1, and PWM_ETRG1.TRGMODE ≠ 0.
The fault 2 is managed as a recoverable fault by the PWMEXTRG2 input trigger when PWM_ETRG2.RFEN = 1,
PWM_ENA.CHID2 = 1, and PWM_ETRG2.TRGMODE ≠ 0.
Recoverable fault 1 and 2 can be taken into account by all channels by enabling the bit FPEx[1/2] in the PWM Fault
Protection Enable registers (PWM_FPEx). However the synchronous channels (see Synchronous Channels) do not
use their own fault enable bits, but those of the channel 0 (bits FPE0[1/2]).
When a recoverable fault is triggered (according to the PWM_ETRGx.TRGMODE setting), the PWM counter of the
affected channels is not cleared (unlike in the classic fault protection mechanism) but the channel outputs are forced
to the values defined by the fields FPVHx and FPVLx in the PWM Fault Protection Value Register 1 (PWM_FPV), as
per table Forcing Values of PWM Outputs by Fault Protection. The output forcing is made asynchronously to the
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 1566