Datasheet

Figure 51-4. Non-Overlapped Center-Aligned Waveforms

OC0

OC1

Period

No overlap

Note: See the figure W

aveform Properties for a detailed description of center-aligned waveforms.

When center-aligned, the channel counter increases up to CPRD and decreases down to 0. This ends the period.

When left-aligned, the channel counter increases up to CPRD and is reset. This ends the period.

Thus, for the same CPRD value, the period for a center-aligned channel is twice the period for a left-aligned channel.

Waveforms are fixed at 0 when:

• CDTY = CPRD and CPOL = 0 (Note that if TRGMODE = MODE3, the PWM waveform switches to 1 at the

external trigger event (see Cycle-By-Cycle Duty Mode)).

• CDTY = 0 and CPOL = 1

Waveforms are fixed at 1 (once the channel is enabled) when:

• CDTY = 0 and CPOL = 0

• CDTY = CPRD and CPOL = 1 (Note that if TRGMODE = MODE3, the PWM waveform switches to 0 at the

external trigger event (see Cycle-By-Cycle Duty Mode)).

The waveform polarity must be set before enabling the channel. This immediately affects the channel output level.

Modifying CPOL in PWM Channel Mode Register while the channel is enabled can lead to an unexpected behavior of

the device being driven by PWM.

In addition to generating the output signals OCx, the comparator generates interrupts depending on the counter

value. When the output waveform is left-aligned, the interrupt occurs at the end of the counter period. When the

output waveform is center-aligned, the bit CES of PWM_CMRx defines when the channel counter interrupt occurs. If

CES is set to ‘0’, the interrupt occurs at the end of the counter period. If CES is set to ‘1’, the interrupt occurs at the

end of the counter period and at half of the counter period.

The figure below illustrates the counter interrupts depending on the configuration.

SAM E70/S70/V70/V71 Family

Pulse W

idth Modulation Controller (PWM)

echnology Inc.

Datasheet

DS60001527D-page 1554