Datasheet

Note:
1.
FPOL field in PWMC_FMR.
51.6 Functional Description
The PWM controller is primarily composed of a clock generator module and 4 channels.
• Clocked by the peripheral clock, the clock generator module provides 13 clocks.
• Each channel can independently choose one of the clock generator outputs.
• Each channel generates an output waveform with attributes that can be defined independently for each channel
through the user interface registers.
51.6.1 PWM Clock Generator
Figure 51-2. Functional View of the Clock Generator Block Diagram
modulo n counter
peripheral clock/2
peripheral clock/4
peripheral clock/16
peripheral clock/32
peripheral clock/64
peripheral clock/8
Divider A clkA
DIVA
PWM_CLK
peripheral clock
peripheral clock/128
peripheral clock/256
peripheral clock/512
peripheral clock/1024
PREA
Divider B clkB
DIVB
PWM_CLK
PREB
Peripheral Clock
The PWM peripheral clock is divided in the clock generator module to provide different clocks available for all
channels. Each channel can independently select one of the divided clocks.
The clock generator is divided into dif
ferent blocks:
• a modulo n counter which provides 11 clocks: f
peripheral clock
, f
peripheral clock
/2, f
peripheral clock
/4, f
peripheral clock
/8,
f
peripheral clock
/16, f
peripheral clock
/32, f
peripheral clock
/64, f
peripheral clock
/128, f
peripheral clock
/256, f
peripheral clock
/512,
f
peripheral clock
/1024
• two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and clkB
Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock to
be divided is made according to the PREA (PREB) field of the PWM Clock register (PWM_CLK). The resulting clock
clkA (clkB) is the clock selected divided by DIVA (DIVB) field value.
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 1551