Datasheet

51. Pulse Width Modulation Controller (PWM)
51.1 Description
The Pulse Width Modulation Controller (PWM) generates output pulses on 4 channels independently according to
parameters defined per channel. Each channel controls two complementary square output waveforms.
Characteristics of the output waveforms such as period, duty-cycle, polarity and dead-times (also called dead-bands
or non-overlapping times) are configured through the user interface. Each channel selects and uses one of the clocks
provided by the clock generator
. The clock generator provides several clocks resulting from the division of the PWM
peripheral clock. External triggers can be managed to allow output pulses to be modified in real time.
All accesses to the PWM are made through registers mapped on the peripheral bus. All channels integrate a double
buffering system in order to prevent an unexpected output waveform while modifying the period, the spread
spectrum, the duty-cycle or the dead-times.
Channels can be linked together as synchronous channels to be able to update their duty-cycle or dead-times at the
same time.
The update of duty-cycles of synchronous channels can be performed by the DMA Controller channel which offers
buffer transfer without processor Intervention.
The PWM includes a spread-spectrum counter to allow a constantly varying period (only for Channel 0). This counter
may be useful to minimize electromagnetic interference or to reduce the acoustic noise of a PWM driven motor.
The PWM provides 8 independent comparison units capable of comparing a programmed value to the counter of the
synchronous channels (counter of channel 0). These comparisons are intended to generate software interrupts, to
trigger pulses on the 2 independent event lines (in order to synchronize ADC conversions with a lot of flexibility
independently of the PWM outputs) and to trigger DMA Controller transfer requests.
PWM outputs can be overridden synchronously or asynchronously to their channel counter.
The PWM provides a fault protection mechanism with 8 fault inputs, capable to detect a fault condition and to
override the PWM outputs asynchronously (outputs forced to ‘0’, ‘1’ or Hi-Z).
For safety usage, some configuration registers are write-protected.
51.2 Embedded Characteristics
• 4 Channels
• Common Clock Generator Providing Thirteen Different Clocks
– A Modulo n Counter Providing Eleven Clocks
– Two Independent Linear Dividers Working on Modulo n Counter Outputs
• Independent Channels
– Independent 16-bit Counter for Each Channel
– Independent Complementary Outputs with 12-bit Dead-Time Generator (Also Called Dead-Band or Non-
Overlapping Time) for Each Channel
– Independent Push-Pull Mode for Each Channel
– Independent Enable Disable Command for Each Channel
– Independent Clock Selection for Each Channel
– Independent Period, Duty-Cycle and Dead-Time for Each Channel
– Independent Double Buffering of Period, Duty-Cycle and Dead-Times for Each Channel
– Independent Programmable Selection of The Output Waveform Polarity for Each Channel, with Double
Buffering
– Independent Programmable Center- or Left-aligned Output Waveform for Each Channel
– Independent Output Override for Each Channel
– Independent Interrupt for Each Channel, at Each Period for Left-Aligned or Center-Aligned Configuration
SAM E70/S70/V70/V71 Family
Pulse W
idth Modulation Controller (PWM)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1546