Datasheet

50.7.12 TC Interrupt Disable Register
Name: TC_IDRx
Offset: 0x28 + x*0x40 [x=0..2]
Reset: –
Property: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No ef
fect.
1: Disables the corresponding interrupt.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
Access
W W W W W W W W
Reset – – – – – – – –
Bit 7 – ETRGS External T
rigger
Bit 6 – LDRBS RB Loading
Bit 5 – LDRAS RA Loading
Bit 4 – CPCS RC Compare
Bit 3 – CPBS RB Compare
Bit 2 – CPAS RA Compare
Bit 1 – LOVRS Load Overrun
Bit 0 – COVFS Counter Overflow
SAM E70/S70/V70/V71 Family
T
imer Counter (TC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1533