Datasheet

Value Description
0
RA Load has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1.
1
RA Load has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 0.
Bit 4 – CPCS RC Compare Status (cleared on read)
Value Description
0
RC Compare has not occurred since the last read of the Status Register.
1
RC Compare has occurred since the last read of the Status Register.
Bit 3 – CPBS RB Compare Status (cleared on read)
Value Description
0
RB Compare has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 0.
1
RB Compare has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 1.
Bit 2 – CPAS RA Compare Status (cleared on read)
Value Description
0
RA Compare has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 0.
1
RA Compare has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 1.
Bit 1 – LOVRS Load Overrun Status (cleared on read)
Value Description
0
Load overrun has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1.
1
RA or RB have been loaded at least twice without any read of the corresponding register since the last
read of the Status Register
, if TC_CMRx.WAVE = 0.
Bit 0 – COVFS Counter Overflow Status (cleared on read)
Value Description
0
No counter overflow has occurred since the last read of the Status Register.
1
A counter overflow has occurred since the last read of the Status Register.
SAM E70/S70/V70/V71 Family
T
imer Counter (TC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1531