Datasheet

Bit 14 – CPCTRG RC Compare T
rigger Enable
Value Description
0
RC Compare has no effect on the counter and its clock.
1
RC Compare resets the counter and starts the counter clock.
Bit 10 – ABETRG TIOAx or TIOBx External T
rigger Selection
Value Description
0
TIOBx is used as an external trigger.
1
TIOAx is used as an external trigger.
Bits 9:8 – ETRGEDG[1:0] External T
rigger Edge Selection
Value Name Description
0
NONE The clock is not gated by an external signal.
1
RISING Rising edge
2
FALLING Falling edge
3
EDGE Each edge
Bit 7 – LDBDIS Counter Clock Disable with RB Loading
Value Description
0
Counter clock is not disabled when RB loading occurs.
1
Counter clock is disabled when RB loading occurs.
Bit 6 – LDBSTOP Counter Clock Stopped with RB Loading
Value Description
0
Counter clock is not stopped when RB loading occurs.
1
Counter clock is stopped when RB loading occurs.
Bits 5:4 – BURST[1:0] Burst Signal Selection
Value Name Description
0
NONE The clock is not gated by an external signal.
1
XC0 XC0 is ANDed with the selected clock.
2
XC1 XC1 is ANDed with the selected clock.
3
XC2 XC2 is ANDed with the selected clock.
Bit 3 – CLKI Clock Invert
Value Description
0
Counter is incremented on rising edge of the clock.
1
Counter is incremented on falling edge of the clock.
Bits 2:0 – TCCLKS[2:0] Clock Selection
T
o operate at maximum peripheral clock frequency, refer to “TC Extended Mode Register”.
Value Name Description
0
TIMER_CLOCK1 Clock selected: internal PCK6 or PCK7 (TC0 only) clock signal (from PMC)
1
TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC)
2
TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC)
3
TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC)
4
TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC)
5
XC0 Clock selected: XC0
6
XC1 Clock selected: XC1
7
XC2 Clock selected: XC2
SAM E70/S70/V70/V71 Family
T
imer Counter (TC)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 1520